The present invention relates to etching and, more particularly, to etching of patterns in surfaces of materials.
In the production of semiconductor devices, for example, it is desirable to etch patterns in the surface of a substrate for producing electronic circuits and the like. One way of performing this in the prior art includes applying a photo resist to the surface and then exposing the surface to light through a mask so that a difference in solubility exists in the photo resist dependent upon whether or not a particular area was exposed to the light. In a subsequent step in the process, one of the differently exposed areas of resist is dissolved to produce a pattern corresponding to the photographic mask. Various further processing steps may be performed.
In integrated circuit manufacture, the density of circuits on a substrate is limited principally by the fineness of features which can be photographically reproduced. In commercial production of integrated circuits, line widths on the order of 3 to 5 microns are achieved. With the use of visible light, it is predicted that a line width of about 0.5 microns may be possible. With shorter wavelengths using, for example X-rays, slightly reduced line widths may be feasible. The theoretical limit on line widths appears to be the wavelength of the irradiation.
Etching using charged particles, such as electrons, disclosed in U.S. Pat. No. 3,615,935 and ions, as disclosed in U.S. Pat. Nos. 4,233,109 and 4,275,286 has limited resolution due to the net electrical charge on these particles which produces Coulomb repulsion mutually between particles and also between particles and the nuclei or electrons of the substrate. The interaction between the charged particles and the substrate, of course, also limits the depth of penetration into the substrate which can be expected when etching with charged particles.
High energy ion bombardment of a substrate which results in chemical alteration of the substrate through nuclear reactions is disclosed in U.S. Pat. Nos. 3,425,111 and 3,967,982. The latter patent also discloses that such high energy ion bombardment produces crystal dislocations, lattice defects and other damage, which must be eliminated by annealing or subsequent heat treatment in the processing.
A further use of neutron bombardment in semiconductor processing is disclosed in U.S. Pat. No. 3,733,222 in which such neutron bombardment is employed to eliminate the inversion layer in a diode between a masking layer and a P-type semi-conductor. This patent has no relationship to etching or the creation of patterns in a substrate, but is a post-formation treatment to improve the performance of the device.